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CY7C1020CV33
512 K (32 K x 16) Static RAM
512 K (32 K x 16) Static RAM
Features

Functional Description
The CY7C1020CV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020CV33 is available in standard 44-pin TSOP Type II package.
Pin- and function-compatible with CY7C1020CV33 Temperature Ranges Commercial: 0 C to 70 C Industrial: -40 C to 85 C Automotive: -40 C to 125 C High speed tAA = 10 ns CMOS for optimum speed/power Low active power 325 mW (max) Automatic power-down when deselected Independent control of upper and lower bits Available in Pb-free and non Pb-free 44-pin TSOP II package

Logic Block Diagram
DATA IN DRIVERS
A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
32K x 16 RAM Array
SENSE AMPS
I/O1-I/O8 I/O9-I/O16
COLUMN DECODER BHE WE CE OE BLE
Cypress Semiconductor Corporation Document Number: 38-05133 Rev. *H
A8 A9 A10 A11 A12 A13 A14
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised December 2, 2010
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CY7C1020CV33
Contents
Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 Electrical Characteristics ................................................. 5 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 6 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Read Cycle No. 1 ........................................................ 7 Read Cycle No. 2 (OE Controlled) .............................. 7 Write Cycle No. 1 (CE Controlled) ............................... 8 Write Cycle No. 2 (BLE or BHE Controlled) ................ 8 Write Cycle No. 3 (WE Controlled, OE LOW) ............. 9 Truth Table ........................................................................ 9 Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagrams .......................................................... 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13
Document Number: 38-05133 Rev. *H
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CY7C1020CV33
Selection Guide
-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial/Industrial Automotive Commercial/Industrial Automotive 10 90 - 5 - -12 12 85 - 5 - -15 15 80 85 5 10 Unit ns mA mA mA mA
Pin Configuration [1]
TSOP II Top View NC A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A4 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC
Note 1. NC pins are not connected on the die.
Document Number: 38-05133 Rev. *H
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CY7C1020CV33
Pin Definitions
Pin Name A0-A14 I/O1-I/O16 NC WE CE BHE, BLE OE TSOP - Pin Number I/O Type Description Address Inputs used to select one of the address locations. Bidirectional Data I/O lines. Used as input or output lines depending on operation. No Connects. Not connected to the die. 5, 4, 3, 2, 18, 44, 43, 42, 27, Input 26, 25, 24, 21, 20, 19 7-10, 13-16, 29-32, 35-38 1, 22, 23, 28 17 6 40, 39 41 Input/Output No Connect
Input/Control Write Enable Input, active LOW. When selected LOW, a Write is conducted. When deselected HIGH, a Read is conducted. Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O16-I/O9, BLE controls I/O8-I/O1. Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system.
VSS VCC
12, 34 11, 33
Power Supply Power Supply inputs to the device.
Document Number: 38-05133 Rev. *H
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CY7C1020CV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ -65 C to +150 C Ambient temperature with power applied ........................................... -55 C to +125 C Supply voltage on VCC to relative GND[2] .....-0.5 V to +4.6 V DC voltage applied to outputs in high Z State[2] .................................. -0.5 V to VCC + 0.5 V DC input voltage[2] ............................... -0.5 V to VCC + 0.5 V Current into outputs (LOW) ......................................... 20 mA Static discharge voltage........................................... > 2001 V (per MIL-STD-883, method 3015) Latch-up current ..................................................... > 200 mA
Operating Range
Range Commercial Industrial Automotive Ambient Temperature 0 C to +70 C -40 C to +85 C -40 C to +125 C VCC 3.3 V 10% 3.3 V 10% 3.3 V 10%
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage[2] Input leakage current GND < VI < VCC Commercial/ Industrial Automotive IOZ Output leakage current GND < VI < VCC, Output Disabled VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC Commercial/ Industrial Automotive ICC VCC operating supply current Automatic CE power-down current --TTL Inputs Automatic CE power-down current --CMOS inputs Commercial/ Industrial Automotive Test Conditions VCC = Min, IOH = -4.0 mA VCC = Min, IOL = 8.0 mA -10 Min 2.4 - 0.3 1 - 1 - - - - - - - Max - 0.4 0.8 +1 - +1 - 90 - 15 - 5 - Min 2.4 - -0.3 -1 - -1 - - - - - - - -12 Max - 0.4 0.8 +1 - +1 - 85 - 15 - 5 - Min 2.4 - -0.3 -1 -20 -1 -20 - - - - - - -15 Max - 0.4 0.8 +1 +20 +1 +20 80 85 15 20 5 10 Unit V V V V A A A A mA mA mA mA mA mA
2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3
ISB1
Max VCC, CE > VIH Commercial/ VIN > VIH or VIN < VIL, Industrial f = fMAX Automotive Max VCC, CE > VCC - 0.3 V, VIN > VCC - 0.3 V, or VIN < 0.3 V, f = 0 Commercial/ Industrial Automotive
ISB2
Capacitance[3]
Parameter CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max 8 8 Unit pF pF
Thermal Resistance[3]
Parameter Description Thermal resistance (Junction to Ambient) Thermal resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 44-pin TSOP-II Unit 76.92 15.86 C/W C/W
JA JC
Notes 2. VIL (min) = -2.0 V and VIH(max) = VCC + 0.5 V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05133 Rev. *H
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CY7C1020CV33
AC Test Loads and Waveforms[4]
3.3 V OUTPUT 30 pF R2 351 GND
Rise Time: 1 V/ns
R 317 3.0 V
ALL INPUT PULSES 90% 10% 90% 10%
High Z characteristics: R 317 3.3 V OUTPUT 5 pF R2 351
(a)
(b)
Fall Time: 1 V/ns
(c)
Switching Characteristics
Over the Operating Range[4] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[7] tPD[7] tDBE tLZBE tHZBE Write Cycle[8] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write cycle time CE LOW to write end Address set-up to write end Address hold from write end Address set-up to write start WE pulse width Data set-up to write end Data hold from write end WE HIGH to low Z[5] WE LOW to high Z[5, 6] Byte enable to end of write 10 8 7 0 0 7 5 0 3 - 7 - - - - - - - - - 5 - 12 9 8 0 0 8 6 0 3 - 8 - - - - - - - - - 6 - 15 10 10 0 0 10 8 0 3 - 9 - - - - - - - - - 7 - ns ns ns ns ns ns ns ns ns ns ns Read cycle time Address to data valid Data hold from address change CE LOW to data valid OE LOW to data valid OE LOW to low Z[5] Z[5, 6] Z[5, 6] OE HIGH to high CE HIGH to high 10 - 3 - - 0 - 3 - 0 - - 0 - - 10 - 10 5 - 5 - 5 - 10 5 - 5 12 - 3 - - 0 - 3 - 0 - - 0 - - 12 - 12 6 - 6 - 6 - 12 6 - 6 15 - 3 - - 0 - 3 - 0 - - 0 - - 15 - 15 7 - 7 - 7 - 15 7 - 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -10 Min Max Min -12 Max Min -15 Max Unit
CE LOW to low Z[5] CE LOW to power-up CE HIGH to power-down Byte enable to data valid Byte enable to low Z Byte disable to high Z
Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. This parameter is guaranteed by design and is not tested. 8. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Document Number: 38-05133 Rev. *H
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CY7C1020CV33
Switching Waveforms
Read Cycle No. 1[9, 10]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE
HIGH IMPEDANCE
IICC CC IISB SB
Notes 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for Read cycle. 11. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05133 Rev. *H
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CY7C1020CV33
Switching Waveforms
(continued)
Write Cycle No. 1 (CE Controlled)[12, 13]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATA I/O tHD
tHA
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA I/O tHD
tHA
Notes 12. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document Number: 38-05133 Rev. *H
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CY7C1020CV33
Switching Waveforms
(continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC ADDRESS
CE
tSCE
tAW tSA WE tBW BHE, BLE tHZWE DATA I/O tSD tHD tPWE
tHA
tLZWE
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1-I/O8 High Z Data out Data out High Z Data in Data in High Z High Z High Z I/O9-I/O16 High Z Data out High Z Data out Data in High Z Data in High Z High Z Power-down Read--All bits Read--Lower bits only Read--Upper bits only Write--All bits Write--Lower bits only Write--Upper bits only Selected, outputs disabled Selected, outputs disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Document Number: 38-05133 Rev. *H
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CY7C1020CV33
Ordering Information
Speed (ns) 15 Ordering Code CY7C1020CV33-15ZSXE CY7C1020CV33-15ZSXET Package Diagram 51-85087 51-85087 Package Type 44-pin TSOP Type II (Pb-free) 44-pin TSOP Type II (Pb-free) Operating Range Automotive Automotive
Ordering Code Definitions
CY7C 1020 C V33 - 15 ZSX E X X = T or Blank T = Tape and Reel; Blank = Tube Temperature Range: E = Automotive Package Type: ZSX = 44-pin TSOP Type II (Pb-free) Speed Grade = 15 ns V33 = 3.3 V Process Technology 0.16 m 1020 = Part Identifier CY7C = Cypress SRAMs
Package Diagrams
Figure 1. 44-pin TSOP II, 51-85087
51-85087 *C
Document Number: 38-05133 Rev. *H
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CY7C1020CV33
Acronyms
Acronym CMOS CE I/O OE SRAM TSOP TTL WE chip enable input/output output enable static random access memory thin small-outline package transistor-transistor logic write enable Description complementary metal oxide semiconductor
Document Conventions
Units of Measure
Symbol ns V A mA mW MHz pF C W % nano seconds Volts micro Amperes milli Amperes milli Watts Mega Hertz pico Farad degree Celcius Watts percent Unit of Measure
Document Number: 38-05133 Rev. *H
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CY7C1020CV33
Document History Page
Document Title: CY7C1020CV33 512 K (32 K x 16) Static RAM Document Number: 38-05133 REV. ** *A *B *C *D *E ECN NO. 109428 115045 117615 262949 334398 493543 Issue Date 12/16/01 05/30/02 08/14/02 See ECN See ECN See ECN Orig. of Change HGK HGK DFP RKF SYT NXR New Data Sheet ICC and ISB1 data modified Pin 1= NC Pin 18 = A4; remove SOJ package option; remove 8ns option. Added Automotive Specs to Data sheet Added Lead-Free Product Information Added note #1 on page #1 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated Ordering Information Table Updated Ordering Information Updated Package Diagram Updated Ordering Information and added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits and updated in new template. Description of Change
*F *G *H
2897691 3057593 3100106
03/23/2010 10/13/2010 12/02/2010
RAME PRAS PRAS
Document Number: 38-05133 Rev. *H
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CY7C1020CV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
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PSoC Solutions
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(c) Cypress Semiconductor Corporation, 2001-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05133 Rev. *H
Revised December 2, 2010
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